PLLMUL=others, PLSRCSEL=0, PLIDIV=00
PLL Clock Control Register
| PLIDIV | PLL Input Frequency Division Ratio Select 0 (00): /1 1 (01): /2 2 (10): /3 3 (11): Setting prohibited |
| PLSRCSEL | PLL Clock Source Select 0 (0): Main clock oscillator 1 (1): HOCO |
| PLLMUL | PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0 0 (others): Setting prohibited |